The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique which is effectively applicable to a semiconductor device which includes resistance elements.
As one of element isolations which electrically isolate element forming regions on a main surface of a semiconductor substrate, there has been known a groove-type element isolation which is referred to as, for example, STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation). This groove-type element isolation is a technique which forms grooves by etching element isolation regions on the main surface of the semiconductor substrate and, thereafter, an insulation film is embedded in the inside of the grooves thus electrically isolating the element forming reigns. The element forming regions which are isolated by the groove-type element isolation are constituted of semiconductor layers (active layers) which are defined in an island shape, and the semiconductor layer has a periphery thereof surrounded by an insulation film which is embedded in the groove. The insulation film is embedded into the grooves such that an insulation film formed of a silicon oxide film, for example is stacked on the main surface of the semiconductor substrate using a CVD (Chemical Vapor Deposition) method in a state that the insulation film is filled in the inside of the grooves and, thereafter, the insulation film formed over the main surface of the semiconductor substrate is removed using, for example, a CMP (Chemical Mechanical Polishing) method so as to allow the insulation film to selectively remain in the grooves.
In the groove-type element isolation which uses the CMP method, when a width of the groove becomes relatively large, a polishing speed of the insulation film is locally increased and hence, a so-called dishing phenomenon in which a center portion of the insulation film which remains in the groove is indented is liable to be easily generated.
Japanese Unexamined Patent Publication No. 2002-158278 discloses a technique which suppresses a dishing phenomenon at the time of removing the insulation film on the main surface of the semiconductor substrate using the CMP method so as to allow the insulation film to selectively remain in the inside of the groove by forming a dummy semiconductor layer (dummy active layer) which differs from the semiconductor layer (active layer) used as the transistor element forming region in the element isolation region on the main surface of the semiconductor substrate.
Japanese Unexamined Patent Publication No. 2002-261244 discloses a technique which suppresses a dishing phenomenon at the time of removing an insulation film on a main surface of a semiconductor substrate using a CMP method so as to allow the insulation film to selectively remain in the inside of the grooves, thus enhancing the accuracy of resistance values of poly-silicon resistance elements formed over the insulation film (element isolation oxide film) in the inside of the groove.